DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 369

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DS3184DK

Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3184DK

Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Size Violation Packet Count (RSPC[15:0]) – Lower 16 bits of 24 bits. Register description
follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Size Violation Packet Count (RSPC[23:16]) - Upper 8 bits of Register.
Receive Size Violation Packet Count (RSPC[23:0]) – These 24 bits indicate the number of packets received with
a packet size violation (below minimum, above maximum, or non-integer number of bytes). The byte count for
these packets is included in the receive aborted byte count register PP.REBCR.
RSPC15
RSPC23
RSPC7
15
15
0
7
0
0
7
0
RSPC14
RSPC22
RSPC6
14
14
0
6
0
0
6
0
PP.RSPCR1
Packet Processor Receive Size Violation Packet Count Register 1
(1,3,5,7)E0h
PP.RSPCR2
Packet Processor Receive Size Violation Packet Count Register 2
(1,3,5,7)E2h
RSPC13
RSPC21
RSPC5
13
13
0
5
0
0
5
0
RSPC12
RSPC20
RSPC4
12
12
0
0
0
0
4
4
369
RSPC11
RSPC19
RSPC3
11
11
0
3
0
0
3
0
RSPC10
RSPC18
RSPC2
10
10
0
2
0
0
2
0
RSPC17
RSPC9
RSPC1
9
0
1
0
9
0
1
0
RSPC16
RSPC8
RSPC0
8
0
0
0
8
0
0
0

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