DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 314

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.11.2 Fractional Receive Side Register Map
The receive side uses three registers.
Table 12-42. Receive Side Register Map
12.11.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Receive Section A Source Select (RSASS) – When 0, Section A of each receive data group will contain
fractional overhead. When 1, Section A of each receive data group will contain payload data.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 0: Receive Data Group Size (RDGS[12:0]) – These 13 bits indicate the number of bits contained within
each receive data group. A values of 0000h and 0001h both result in a receive data group size of one bit.
(1,3,5,7)4Ch
(1,3,5,7)4Ah
(1,3,5,7)4Eh
(1,3,5,7)48h
ADDRESS
RDGS7
15
15
—
—
—
0
7
0
0
7
0
FRAC.RDGSR
FRAC.RSASR
FRAC.RCR
REGISTER
—
RDGS6
14
14
—
—
—
0
6
0
0
6
0
FRAC.RCR
Fractional Receive Control Register
(1,3,5,7)48h
FRAC.RDGSR
Fractional Receive Data Group Size Register
(1,3,5,7)4Ah
Fractional Receive Control Register
Fractional Receive Data Group Size Register
Fractional Receive Section A Size Register
Unused
RDGS5
13
13
—
—
—
0
5
0
0
5
0
REGISTER DESCRIPTION
RDGS12
RDGS4
12
—
12
—
0
0
0
0
4
4
314
RDGS11
RDGS3
11
11
—
—
0
3
0
0
3
0
RDGS10
RDGS2
10
10
—
—
0
2
0
0
2
0
RDGS9
RDGS1
—
—
9
0
1
0
9
0
1
0
RDGS8
RDGS0
RSASS
—
8
0
0
0
8
0
0
0