DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 350
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DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 350 of 400
- Download datasheet (4Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: Out Of Sync Change Latched (OOSL) – This bit is set when the OOS bit in the CP.RSR register changes
state.
Bit 10: Change Of Cell Delineation Latched (COCDL) – This bit is set when the data path cell counters are
updated with a new cell delineation that is different from the previous cell delineation.
Bit 9: Out Of Cell Delineation Change Latched (OCDCL) – This bit is set when the OCD bit in the CP.RSR
register changes state. Note: Immediately after a reset, this bit will be set to one.
Bit 8: Loss Of Cell Delineation Change Latched (LCDCL) – This bit is set when the LCD bit in the CP.RSR
register changes state
Bit 7: Receive Errored Header Cell Latched (RECL) – This bit is set when a cell with an errored header is
discarded.
Bit 6: Receive Corrected Header Cell Latched (RCHL) – This bit is set when a cell with a single header error is
corrected.
Bit 5: Receive Idle Cell Detection Latched (RIDL) – This bit is set when an idle cell is discarded.
Bit 4: Receive Unassigned Cell Detection Latched (RUDL) – This bit is set when an unassigned cell is
discarded.
Bit 3: Receive Invalid Cell Detection Latched (RIVDL) – This bit is set when an invalid cell is discarded.
Bit 2: Receive Errored Header Cell Count Latched (RECCL) – This bit is set when the RECC bit in the CP.RSR
register transitions from zero to one.
Bit 1: Receive Header Pattern Cell Count Latched (RHPCL) – This bit is set when the RHPC bit in the CP.RSR
register transitions from zero to one.
Bit 0: Receive Corrected Header Cell Count Latched (RCHCL) – This bit is set when the RCHC bit in the
CP.RSR register transitions from zero to one.
RECL
15
—
7
RCHL
14
—
6
CP.RSRL
Cell Processor Receive Status Register Latched
(1,3,5,7)D0h
RIDL
13
—
5
RUDL
12
—
4
350
RIVDL
OOSL
11
3
COCDL
RECCL
10
2
OCDCL
RHPCL
9
1
RCHCL
LCDCL
8
0
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