DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 272

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.9.2 Trail Trace Receive Side Register Map
The receive side uses seven registers.
Table 12-32. Trail Trace Receive Side Register Map
12.9.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Receive Multiframe Alignment Disable (RMAD) – When 0, multiframe alignment is performed. When 1,
multiframe alignment is disabled and the trail trace bytes are stored starting with a random byte.
Bit 2: Receive Expected Trail Trace Comparison Enable (RETCE) – When 0, expected trail trace comparison is
disabled. When 1, expected trail trace comparison is performed. Note: When the RMAD bit is one, expected trail
trace comparison is disabled regardless of the setting of this bit.
Bit 1: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for trail trace
processing. When 1, the incoming data is inverted before being passed on for trail trace processing.
Bit 0: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is the
MSB TT.RIR.RTD[7] of the byte). When 1, bit reordering is enabled (The first bit received is the LSB
TT.RIR.RTD[0] of the byte).
(0,2,4,6)FAh
(0,2,4,6)FCh
(0,2,4,6)FEh
(0,2,4,6)F0h
(0,2,4,6)F2h
(0,2,4,6)F4h
(0,2,4,6)F6h
(0,2,4,6)F8h
ADDRESS
15
—
—
0
7
0
REGISTER
TT.RSRIE
TT.RTIAR
TT.RSRL
TT.RCR
TT.RSR
TT.RIR
TT.EIR
—
14
—
—
0
6
0
Trail Trace Receive Control Register
Trail Trace Receive Identifier Address Register
Trail Trace Receive Status Register
Trail Trace Receive Status Register Latched
Trail Trace Receive Status Register Interrupt Enable
Unused
Trail Trace Receive Identifier Register
Trail Trace Expected Identifier Register
TT.RCR
Trail Trace Receive Control Register
(0,2,4,6)F0h
Reserved
13
—
0
5
0
REGISTER DESCRIPTION
Reserved
12
—
0
0
4
272
RMAD
11
—
0
3
0
RETCE
10
—
0
2
0
RDIE
—
9
0
1
0
RBRE
—
8
0
0
0