DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 352

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit 1: Receive Header Pattern Cell Count Interrupt Enable (RHPCIE) – This bit enables an interrupt if the
RHFCL bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive Corrected Header Cell Count Interrupt Enable (RCHCIE) – This bit enables an interrupt if the
RCHCL bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Cell Count (RCC[15:0]) – Lower 16 bits of 24 bits. Register description follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Cell Count (RCC[23:16]) - Upper 8 bits of Register.
Receive Cell Count (RCC[23:0]) – These 24 bits indicate the number of cells stored in the receive FIFO. Note:
Cells discarded due to system loopback or an overflow condition will be included in this count. This register is
updated via the PMU signal (see Section 10.4.5).
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RCC15
RCC23
RCC7
15
15
—
0
7
0
0
7
0
RCC14
RCC22
RCC6
14
14
—
0
6
0
0
6
0
CP.RCCR1
Cell Processor Receive Cell Count Register 1
(1,3,5,7)D4h
CP.RCCR2
Cell Processor Receive Cell Count Register 2
(1,3,5,7)D6h
RCC13
RCC21
RCC5
13
13
—
0
5
0
0
5
0
RCC12
RCC20
RCC4
12
12
—
0
0
0
0
4
4
352
RCC11
RCC19
RCC3
11
11
—
0
3
0
0
3
0
RCC10
RCC18
RCC2
10
10
—
0
2
0
0
2
0
RCC17
RCC9
RCC1
—
9
0
1
0
9
0
1
0
RCC16
RCC8
RCC0
—
8
0
0
0
8
0
0
0