DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 7

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13 JTAG INFORMATION
14 PIN ASSIGNMENT
15 PACKAGE INFORMATION
16 PACKAGE THERMAL INFORMATION
17 DC ELECTRICAL CHARACTERISTICS
18 AC TIMING CHARACTERISTICS
19 REVISION HISTORY
12.11 F
12.12 DS3/E3 PLCP............................................................................................................................316
12.13 FIFO R
12.14 C
13.1 JTAG D
13.2 JTAG TAP C
13.3 JTAG I
13.4 JTAG ID C
13.5 JTAG F
13.6 IO P
15.1 400-L
18.1 F
18.2 L
18.3 M
18.4 O
18.5 S
18.6 M
18.7 CLAD J
18.8 LIU I
18.9 JTAG I
12.10.4 Receive G.751 E3 Register Map ....................................................................................................... 291
12.10.5 Transmit G.832 E3 Register Map ...................................................................................................... 297
12.10.6 Receive G.832 E3 Register Map ....................................................................................................... 300
12.10.7 Transmit Clear Channel ..................................................................................................................... 309
12.10.8 Receive Clear Channel ...................................................................................................................... 310
12.11.1 Fractional Transmit Side Register Map.............................................................................................. 312
12.11.2 Fractional Receive Side Register Map............................................................................................... 314
12.12.1 Transmit Side PLCP........................................................................................................................... 316
12.12.2 Receive Side PLCP Register Map ..................................................................................................... 320
12.13.1 Transmit FIFO Register Map ............................................................................................................. 331
12.13.2 Receive FIFO Register Map .............................................................................................................. 335
12.14.1 Transmit Cell Processor Register Map .............................................................................................. 338
12.14.2 Receive Cell Processor...................................................................................................................... 345
12.14.3 Transmit Packet Processor Register Map ......................................................................................... 357
12.14.4 Receive Packet Processor Register Map .......................................................................................... 362
18.8.1 Waveform Templates ......................................................................................................................... 393
18.8.2 LIU Input/Output Characteristics........................................................................................................ 397
INE
RACTIONAL
RACTIONAL
YSTEM
ELL
VERHEAD
ISCELLANEOUS
ICRO
INS
NTERFACE
/P
I
NTERFACE
EAD
ACKET
NSTRUCTION
I
NTERFACE
EGISTERS
NTERFACE
UNCTIONAL
ITTER
ESCRIPTION
......................................................................................................................................376
I
NTERFACE
TE-PBGA (27
ODES
P
DS3/E3 ..................................................................................................................312
P
ORT
ONTROLLER
C
P
ORT
ROCESSOR
HARACTERISTICS
AC C
AC C
.........................................................................................................................376
P
........................................................................................................................331
AC C
AC C
IN
AC C
C
T
....................................................................................................................372
AC C
R
HARACTERISTICS
IMING
AC C
HARACTERISTICS
EGISTER AND
HARACTERISTICS
HARACTERISTICS
HARACTERISTICS
HARACTERISTICS
MM X
S
HARACTERISTICS
..........................................................................................................376
HARACTERISTICS
.........................................................................................................338
TATE
27
M
MM
................................................................................................393
ACHINE
I
, 1.27
NSTRUCTIONS
.........................................................................................386
........................................................................................393
.......................................................................................386
.....................................................................................387
....................................................................................399
...................................................................................390
MM
D
.................................................................................388
................................................................................387
ESCRIPTION
7
P
ITCH
......................................................................375
) (56-G6003-003) .......................................380
.............................................................373
372
377
380
381
382
384
400