PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 120

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

process is:
PIC32MX3XX/4XX
7.4.1
The user can program one row of program Flash memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
1.
2.
3.
4.
EXAMPLE 7-1:
DS61143C-page 118
unsigned int NVMUnlock (unsigned int nvmop)
{
}
unsigned int NVMErasePage(void* address)
{
}
Read eight rows of program memory
(1024 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the page (see Example 7-1):
Write the first 128 words from data RAM into the
program memory buffers (see Example 7-1).
unsigned int status;
// Suspend or Disable all Interrupts
asm volatile (“di %0” : “=r” (status));
// Enable Flash Write/Erase Operations and Select
// Flash operation to perform
NVMCON = 0x8000 \ nvmop;
// Write Keys
NVMKEY = 0xAA996655;
NVMKEY = 0x556699AA;
// Start the operation using the Set Register
NVMCONSET = 0x8000;
// Wait for operation to complete
while (NVMCON & 0x8000);
// Restore Interrupts
if (status & 0x00000001
else
// Return NVMERR and LVDERR Error Status Bits
return (NVMCON & 0x3000)
unsigned int res;
// Set NVMADDR to the Start Address of page to erase
NVMADDR = (unsigned int) address;
// Unlock and Erase Page
res = NVMUnlock(0x4004);
// Return Result
return res;
asm volatile (“ei”);
asm volatile (“di”);
PROGRAMMING ALGORITHM
ERASING FLASH PAGE
Preliminary
5.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete.
Repeat steps 4 and 5, using the next available
128 words from the block in data RAM by incre-
menting
NVMASRCADDR, until all 1024 instructions are
written back to Flash memory.
the
value
© 2008 Microchip Technology Inc.
in
NVMADDR
and