PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 234

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
10.5
The Chaining mode is enabled by setting the Chaining
Enable it CHCEN bit (DCHxCON<5>) and Chaining
Direction bit CHCHNS (DCHxCON<8>).
Channel chaining is an enhancement to the DMA
channel operation.
A good usage is for transferring data packets from one
peripheral to memory and then from memory to
another peripheral. This module is also useful for
implementing data acquisition in multiple buffers.
Chaining mode features:
• A channel (slave channel) can be chained to an
• At this point, any event on the slave channel will
• Channels are chained in natural priority order
• An important feature of the DMA controller is the
10.5.1
The Chaining mode is an option for use when perform-
ing DMA transfers. Therefore, the steps needed in
Chaining mode are identical to those used in basic
DMA configuration, with the following differences
(refer to Section 10.3.1 “Basic Transfer Mode Con-
figuration”):
• Two different channels have to be configured and
Refer to Example 10-3.
10.6
The Auto-Enable mode is enabled by setting the
CHAEN bit (DCHxCON<4>).
DS61143C-page 232
adjacent channel (master channel). When the
master channel completes a block transfer the
slave channel will be enabled.
initiate a cell transfer. If the channel has an event
pending, a cell transfer will begin immediately.
where channel 0 has the highest priority and
channel 3 the lowest. A specific channel can be
enabled by an adjacent channel, either higher, or
lower, in natural order, by configuring the
CHCHNS (DCHxCON<8>) bit. Chaining must be
enabled, CHCHN (DCHxCON<5>) = 1.
ability to allow events while the channel is dis-
abled using the CHAED (DCHxCON<6>) bit. This
bit is particularly useful in Chained mode where
the slave channel needs to be ready to start a
transfer as soon as the channel is enabled by the
master channel.
the slave channel has to have chaining enable
(CHCHN) and chaining direction (CHCHNS) set.
Channel Chaining Mode
Channel Auto-Enable Mode
CHAINING MODE CONFIGURATION
Preliminary
Channel auto-enable function is an enhancement to
the DMA channel operation.
The channel auto-enable can be used to keep a chan-
nel active, even if a block transfer completes or a pat-
tern match occurs. This prevents the user from having
to re-enable the channel each time a block transfer
completes. This mode is useful for applications that do
repeated pattern matching.
10.6.1
The Auto-Enable mode is an extra option for use when
performing DMA transfers. Therefore, the steps
needed in Auto-Enable mode are identical to those
used in basic DMA configuration, with the following dif-
ferences (refer to Section 10.3.1 “Basic Transfer
Mode Configuration”):
• The CHAEN bit has to be set before enabling the
• The channel will behave as normal except that
• Normal block transfer completion is defined as:
• As before, the Channel Pointers will be reset.
channel (setting the CHEN bit (DCHxCON<7>)).
normal termination of a transfer will not result in
the channel being disabled.
- block transfer complete
- pattern match detect
AUTO-ENABLE MODE
CONFIGURATION
© 2008 Microchip Technology Inc.