PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 349

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

EXAMPLE 14-5:
14.3.8
In this mode, the timer clock source is the internal
PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
The TxCK pin provides the gating mechanism to
enable and disable the timer counting, TGATE
(TxCON<7>) = 1. The 32-bit TMRxy Count register is
enabled on the rising edge of the TxCK pin and incre-
ments on every internal PBCLK cycle when the timer
clock prescale <TCKPS> is 1:1.
The timer increments until the TMRxy Count register
matches the PRxy register value. The TMRxy Count
register resets to 0x00000000 on the next PBCLK clock
cycle. A timer match event is not generated. The timer
continues to increment and repeat the period match
until the falling edge of the TxCK pin or the timer is dis-
abled. On the falling edge of the gate signal, a timer
gate event is generated and the TMRxy Count register
stops counting, but is not reset to 0x00000000. The
TMRxy Count register must be reset in software. For
further details regarding timer events and interrupts,
see Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRxy
Count register increments on every Nth timer clock
cycle. For further details regarding timer prescaler,
refer to Section 14.3.9 Timer Clock Prescaler.
The following steps should be performed to properly
configure the timer peripheral for Gated Timer mode
operation:
1.
2.
3.
4.
5.
6.
© 2008 Microchip Technology Inc.
T2CON = 0x0;
T3CON = 0x0;
T2CONSET = 0x006A //32-bit mode,
TMR2 = 0x0;
PR2 = 0xFFFFFFFF; // Load PR2 and PR3
T2CONSET = 0x8000; // Start timer
Note:
Clear control bit, ON (TxCON<15>) = 0, to
disable timer.
Set control bit, T32 (TxCON<3>).
Select the desired timer prescaler using bits
TCKPS<2:0> (TxCON<6:4>).
Set control bit, TCS (TxCON<1>) = 0, to select
the internal clock source.
Set control bit, TGATE (TxCON<7>) = 1.
Clear Timer register, TMRx.
SYNCHRONOUS INTERNAL 32-BIT
GATED TIMER
TxCK pins not available on 64-pin devices.
//Stop Timer2 and clear
//Stop Timer3 and clear
SYNCHRONOUS
EXTERNAL 32-BIT TIMER
INITIALIZATION
//external clock,
//prescale=1:64
// Clear TMR2 and TMR3
// Same as TMR2 = 0x0
// Same as PR2=0xFFFFFFFF
Preliminary
7.
8.
EXAMPLE 14-6:
14.3.9
Timer
(TxCON<6:4>), are used to divide the timer clock
source permitting the TMR register to increment on
every 1, 2, 4, 8, 16, 32, 64, or 256 (PBCLK or external)
clock cycles. For example, if the clock prescale is 1:8,
then the timer increments on every 8th timer clock
cycle.
14.3.10
Associated with the clock prescale selection bits is a
prescale counter. The timer prescale counter is cleared
when any of the following conditions occur:
1.
2.
3.
• When the timer clock source is external and the
• After a timer match event (TMRx = PRx) and
T4CON = 0x0;
T5CON = 0x0;
T4CONSET = 0x00C8; //32-bit mode,
TMR4 = 0x0;
PR4 = 0xFFFFFFFF;
T4CONSET = 0x8000; //Start 32-bit timer
Note:
timer clock prescale = N (other than 1:1), 2 to 3
external clock cycles are required, after the timer
ON bit is set = 1, before the TMRx Count register
increments.
depending on the timer clock prescale setting N
(other than 1:1), the timer will require N additional
(PBCLK or external) clock cycles before the
TMRx Counter register resets to 0x0000. Reading
the TMRx Count register just after the timer match
event, but before the TMRx Count register is
reset, will return the timer match value.
Load Period register, PRx, with desired 32-bit
match value.
Set control bit, ON (TxCON<15>) = 1, to enable
timer.
Any device Reset, except a Power-on Reset.
The timer is disabled.
Any write to the TMR register.
PIC32MX3XX/4XX
clock
prescaler.
TIMER CLOCK PRESCALER
CONSIDERATIONS
When the timer clock source is external and
the timer clock prescale = N (other than
1:1), 2 to 3 external clock cycles are
required to reset and synchronize the
prescale
SYNCHRONOUS
INTERNAL 32-BIT GATED
TIMER INITIALIZATION
//Same as PR4 =0xFFFFFFFF
//Stop Timer4 and clear
//Stop Timer5 and clear
//gate enable,
//internal clock,
//1:16 prescale
//Clear TMR4 and TMR5
//Same as TMR4 = 0x0
//Load PR4 and PR5 regs
bits,
DS61143C-page 347
TCKPS<1:0>