PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 246

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
11.14 U1FRMH and U1FRML Registers
U1FRMH
Register 11-14) are read-only registers. The frame
number is formed by concatenating the two 8-bit regis-
ters. The high-order byte is in the U1FRMH register,
and the low-order byte is in U1FRML.
11.15 U1TOK Register
U1TOK (Register 11-15) is a read/write register
required when the module operates as a host. It is used
to specify the token type, PID<3:0> (Packet ID), and
the endpoint, EP<3:0>, being addressed by the host
processor. Writing to this register triggers a host
transaction.
11.16 U1SOF Register
U1SOF (Register 11-16) threshold is a read/write reg-
ister that contains the count bits of the Start-of-Frame
(SOF) threshold value, and are used in Host mode only.
To prevent colliding a packet data with the SOF token
that is sent every 1 ms, the USB module will not send
any new transactions within the last U1SOF byte times.
The USB module will complete any transactions that
are in progress. In Host mode, the SOF interrupt occurs
when this threshold is reached, not when the SOF
occurs. In Device mode, the interrupt occurs when a
SOF is received. Transactions started within the SOF
threshold are held by the USB module until after the
SOF token is sent.
11.17 U1BDTP1, U1BDTP2 and
These registers (Register 11-17, Register 11-18 and
Register 11-19) are read/write registers that define the
upper 23 bits of the 32-bit base address of the Buffer
DS61143C-page 244
U1BDTP3
and
U1FRML
(Register 11-13
and
Preliminary
Descriptor Table (BDT) in the system memory. The
BDT is forced to be 512 byte-aligned. This register
allows relocation of the BDT in real time.
11.18 U1CNFG1 Register
U1CNFG1 (Register 11-20) is a read/write register that
controls the Debug and Idle behavior of the module.
The register must be preprogrammed prior to enabling
the module.
11.19 U1EP0-U1EP15
These registers control the behavior of the correspond-
ing endpoint.
11.20 Associated Registers
The following registers are not part of the USB module
but are associated with module operation.
• IEC1: Interrupt Enable Control Register
• IFS1: Interrupt Flag Status Register
• DEVCFG2: Device Configuration Word 2
• OSCCON: Oscillator Control Register (Register 4-
11.21 Clearing USB OTG Interrupts
Unlike other device-level interrupts, the USB OTG
interrupt status flags are not freely writable in software.
All USB OTG flag bits are implemented as hardware-
set bits. These bits can only be cleared in software by
writing a ‘1’ to their locations. Writing a ‘0’ to a flag bit
has no effect.
(Register 11-22)
(Register 8-5)
(Register 27-3)
1)
Note:
Throughout this section, a bit that can only
be cleared by writing a ‘1’ to its location is
referred to as “Write ‘1’ to clear bit”. In reg-
ister descriptions, this function is indicated
by the descriptor ‘K’.
© 2008 Microchip Technology Inc.