PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 441

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 20-2:
© 2008 Microchip Technology Inc.
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1:
2:
3:
4:
5:
Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 T
a write operation; WAITB = 1 T
When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not
subject to auto-increment/decrement.
In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins
PMD<7:0> are active when MODE16 = 0.
On 64-pin devices, data pins PMD<15:8> are not available.
The PMADDR register is always incremented/decremented by 1, regardless of the transfer data width.
MODE1:MODE0: Parallel Port Mode Select bits
11 =Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<15:0>)
10 =Master Mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<15:0>)
01 =Addressable Slave Mode, control signals (PMRD, PMWR, PMCS, PMD<7:0>, PMA<1:0>)
00 =Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS, PMD<7:0>)
WAITB1:WAITB0: Data Setup to Read/Write Strobe Wait States bits
11 =Data wait of 4 T
10 =Data wait of 3 T
01 =Data wait of 2 T
00 =Data wait of 1 T
WAITM3:WAITM0: Data Read/Write Strobe Wait States bits
1111 =Wait of 16 T
...
0001 =Wait of 2 T
0000 =Wait of 1 T
WAITE1:WAITE0: Data Hold After Read/Write Strobe Wait States bits
11 =Wait of 4 T
10 =Wait of 3 T
01 =Wait of 2 T
00 =Wait of 1 T
for Read operations:
11 =Wait of 3 T
10 =Wait of 2 T
01 =Wait of 1 T
00 =Wait of 0 T
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
(
(
DEFAULT
DEFAULT
PB
PB
PB
PB
PB
(
DEFAULT
; multiplexed address phase of 4 T
; multiplexed address phase of 3 T
; multiplexed address phase of 2 T
; multiplexed address phase of 1 T
PBCLK
)
)
)
cycle, WAITE = 0 T
Preliminary
PBCLK
PIC32MX3XX/4XX
PB
PB
PB
PB
cycles for a read operation.
(
DEFAULT
(1)
)
(1)
(3,4)
(3,4)
DS61143C-page 439
PBCLK
cycle for