PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 555

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.3
The WDT will cause an NMI or a device Reset when it
expires. The Power Save mode of the device
determines which event occurs. The PWRT does not
generate interrupts or Resets.
26.3.1
When the WDT expires and the device is not in Sleep
or Idle, a device Reset is generated. The CPU code
execution jumps to the device Reset vector and the
Registers and Peripherals are forced to their Reset
values.
To detect a WDT Reset, the WDTO (RCON<4>),
SLEEP (RCON<3>) and IDLE (WDTCON<2>) bits
must be tested. If the WDTO bit is a ‘1’, the event was
do to a WDT time-out. The SLEEP and IDLE bits can
then be tested to determine if the WDT event occurred
while the device was awake or if it was in Sleep or Idle.
EXAMPLE 26-1:
© 2008 Microchip Technology Inc.
//This code fragment assumes the WDT was not enabled by the device configuration
// The Postscaler value must be set with the device configuration
WDTCONSET = 0x8000;// Turn on the WDT
main
{
}
Interrupts and Resets
WDTCONSET = 0x01;// Service the WDT
... User code goes here ...
WATCHDOG TIMER RESET
SAMPLE WDT INITIALIZATION AND SERVICING
Preliminary
26.3.2
When the WDT expires in Sleep or Idle, a NMI is gen-
erated. The NMI causes the CPU code execution to
jump to the device Reset vector. Though the NMI share
the same vector as a device Reset, registers and
peripherals are not reset.
To detect a wake from a Power Save mode by WDT, the
WDTO (RCON<4>), SLEEP (RCON<3>) and IDLE
(WDTCON<2>) bits must be tested. If the WDTO bit is
a ‘1’ the event was caused by a WDT time-out. The
SLEEP and IDLE bits can then be tested to determine
if the WDT event occurred in Sleep or Idle.
To cause a WDT time-out in Sleep to act like an inter-
rupt, a return from interrupt instruction may be used in
the start-up code after the event was determined to be
a WDT wake-up. This will cause code execution to con-
tinue with the opcode following the WAIT instruction
that put the device into Power Save mode. See
Example 26-1.
PIC32MX3XX/4XX
WATCHDOG TIMER NMI
DS61143C-page 553