PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 412

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
REGISTER 18-1:
DS61143C-page 410
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A10M: 10-bit Slave Address Flag bit
1 = I2CxADD is a 10-bit slave address
0 = I2CADD is a 7-bit slave address
DISSLW: Slew Rate Control Disable bit
1 = Slew rate control disabled for Standard Speed mode (100 kHz); also disabled for 1 MHz mode
0 = Slew rate control enabled for High-Speed mode (400 kHz)
SMEN: SMBus Input Levels Disable bit
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
GCEN: General Call Enable bit
In I
1 = Enable interrupt when a general call address is received in I2CSR. Module is enabled for
0 = General call address disabled
STREN: SCL Clock Stretch Enable bit
In I
1 = Enable clock stretching
0 = Disable clock stretching
ACKDT: Acknowledge Data bit
In I
user initiates an Acknowledge sequence at the end of a receive.
1 = A NACK is sent
0 = ACK is sent
ACKEN: Acknowledge Sequence Enable bit
In I
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit; cleared by
0 = Acknowledge sequence idle
RCEN: Receive Enable bit
In I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit
In I
1 = Initiate Stop condition on SDA and SCL pins; cleared by module
0 = Stop condition idle
RSEN: Restart Condition Enable bit
In I
1 = Initiate Restart condition on SDA and SCL pins; cleared by module
0 = Restart condition idle
SEN: Start Condition Enable bit
In I
1 = Initiate Start condition on SDA and SCL pins; cleared by module
0 = Start condition idle
2
2
2
2
2
2
2
2
C Slave mode only
C Slave mode only; used in conjunction with SCLREL bit.
C Master mode only; applicable during master receive
C Master mode only.
C Master mode only.
C Master mode only.
C Master mode only.
C Master mode only; applicable during master receive. Value that will be transmitted when the
reception
module
I2C
X
CON: I
2
C™ CONTROL REGISTER (CONTINUED)
2
C, automatically cleared by module at end of 8-bit receive data byte
Preliminary
© 2008 Microchip Technology Inc.