PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 291

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.
7.
8.
9.
10. Software reads the appropriate BD, completes
11.28.1
Perform the following steps to receive an IN token in
Device mode:
1.
2.
3.
4.
© 2008 Microchip Technology Inc.
Note:
The module issues, or waits for, a handshake
PID (ACK, NAK, STALL), unless the endpoint is
setup as an isochronous endpoint (EPHSHK bit
UEPMx<0> is cleared).
The module updates the BD, and writes the
UOWN bit to ‘0’ (SW owned).
The module updates the U1STAT register, and
sets the TRNIF interrupt.
Software reads the U1STAT register, and deter-
mines the endpoint and direction for the transac-
tion.
all necessary processing, and clears the TRNIF
interrupt.
Attach to a USB host and enumerate as
described in Chapter 9 of the USB 2.0
specification.
Populate the data buffer with the data to send to
the host.
In the appropriate (EVEN or ODD) transmit buf-
fer descriptor for the desired endpoint:
a)
b)
c)
When the USB module receives an IN token, it
automatically transmits the data in the buffer.
Upon completion, the module updates the Sta-
tus bit field (BDnSTAT), clears the UOWN bit
and sets the transfer complete interrupt
(U1IR<TRNIF>).
Set up the control bit field (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
Set up the address bit field (BDnADR) with
the starting address of the data buffer.
Set the UOWN bit field to ‘1’.
For transmitted (IN) transactions (host
reading data from the device), the read
data must be ready when the Host begins
USB signaling. Otherwise, the USB mod-
ule will send a NAK handshake if UOWN is
‘0’.
RECEIVING AN IN TOKEN IN
DEVICE MODE
Preliminary
11.28.2
Perform the following steps to receive an OUT token in
Device mode:
1.
2.
3.
4.
11.29 Host Mode Operation
In Host mode, only Endpoint 0 is used (all other end-
points should be disabled). Since the host initiates all
transfers, the BD does not require immediate initializa-
tion. However, the BDs must be configured before a
transfer is initiated – which is done by writing to the
U1TOK register.
The following sections describe how to perform com-
mon Host mode tasks. In Host mode, USB transfers
are invoked explicitly by the host software. The host
software is responsible for initiating the setup, data,
and status stages of all control transfers. The acknowl-
edge (ACK or NAK) is generated automatically by the
hardware, based on the CRC. Host software is also
responsible for scheduling packets so that they do not
violate USB protocol. All transfers are performed using
the Endpoint 0 Control register (U1EP0) and BDs.
Attach to a USB host and enumerate as
described in Chapter 9 of the USB 2.0
specification.
Create a data buffer with the amount of data you
are expecting from the host.
In the appropriate (EVEN or ODD) transmit buf-
fer descriptor for the desired endpoint:
a)
b)
c)
When the USB module receives an OUT token,
it will automatically receive the data the host
sent into the buffer. Upon completion, the mod-
ule updates the Status bit field (BDnSTAT),
clears the UOWN bit and sets the transfer
complete interrupt (U1IR<TRNIF>).
PIC32MX3XX/4XX
Set up the Status bit field (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
Set up the address bit field (BDnADR) with
the starting address of the data buffer.
Set the UOWN bit of the Status bit field to
‘1’.
RECEIVING AN OUT TOKEN IN
DEVICE MODE
DS61143C-page 289