PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 240

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
10.10 DMA Interrupts
The DMA device has the ability to generate interrupts
reflecting the events that occur during the channel’s
data transfer. The different kinds of DMA interrupt flags
are:
• CHERIF (DCHxINT<0>): Channel Error
• CHTAIF (DCHxINT<1>): Channel Abort interrupts,
• CHBCIF (DCHxINT<3>): Channel Block complete
• CHCCIF (DCHxINT<2>): Channel Cell complete
• CHSDIF (DCHxINT<7>): Channel Source pointer
• CHSHIF (DCHxINT<6>): Channel Source pointer
• CHDDIF (DCHxINT<5>): Channel Destination
• CHDHIF (DCHxINT<4>): Channel Destination
DS61143C-page 238
interrupts, enabled using CHERIE
(DCHxINT<16>).
enabled using CHTAIE (DCHxINT<17>).
interrupts, enabled using CHBCIE
(DCHxINT<19>).
interrupts, enabled using CHCCIE
(DCHxINT<18>).
reached the end of the source, enabled by
CHSDIE (DCHxINT<23>).
reached midpoint of the source, enabled by
CHSHIE (DCHxINT<22>).
Pointer reached the end of the destination,
enabled by CHDDIE (DCHxINT<21>)
Pointer reached midpoint of the destination,
enabled by CHDHIE (DCHxINT<20>).
Preliminary
All the interrupts belonging to a DMA channel map to
the corresponding channel interrupt vector.
The corresponding interrupt flags are:
• DMA0IF (IFS1<16>)
• DMA1IF (IFS1<17>)
• DMA2IF (IFS1<18>)
• DMA3IF (IFS1<19>)
A DMA channel is enabled as a source of interrupts via
the respective DMA interrupt enable bits:
• DMA0IE (IEC1<16>)
• DMA1IE (IEC1<17>)
• DMA2IE (IEC1<18>)
• DMA3IE (IEC1<19>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• DMA0IP<2:0> (IPC9<4:2>), DMA0IS<1:0>
• DMA1IP<2:0> (IPC9<12:10>), DMA1IS<1:0>
• DMA2IP<2:0> (IPC9<20:18>), DMA2IS<1:0>
• DMA3IP<2:0> (IPC9<28:26>), DMA3IS<1:0>
In addition to enabling the DMA interrupts, Interrupt
Service Routines (ISRs) are required for each different
interrupt
Example 10-7.
All these interrupt flags must be cleared in software.
(IPC9<1:0>).
(IPC9<9:8>).
(IPC9<17:16>).
(IPC9<25:24>).
Note:
vector
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
used.
© 2008 Microchip Technology Inc.
See
Example 10-6
and