PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.32 Completing a Control Transaction
Complete all of the following steps to discover a con-
nected device:
1.
2.
3.
4.
5.
6.
7.
8.
© 2008 Microchip Technology Inc.
Set up the Endpoint Control register for bidirec-
tional control transfers, U1EP0<4:0> = 0x0D.
Place an 8-byte of the device setup packet in the
appropriate memory buffer. See Chapter 9 of
the USB 2.0 specification for information on the
device framework command set.
Initialize the current (EVEN or ODD) TX EP0 BD
to transfer the 8 byte device framework com-
mand (for example, a GET DEVICE DESCRIP-
TOR command).
a)
b)
Set the USB address of the target device in the
address register U1ADDR<6:0>. After a USB
bus Reset, the device USB address will be zero.
After enumeration, it must be set to another
value, between 1 and 127, by the host software.
Write the token register with a SETUP command
to Endpoint 0, the target device’s default control
pipe (U1TOK = 0xD0). This will initiate a SETUP
token on the bus followed by a data packet. The
device handshake will be returned in the PID
field of BD0STAT after the packets complete.
When the module updates BD0STAT, a transfer
done interrupt will be asserted (U1IR<TRNIF>).
This completes the setup stage of the setup
transfer as described in Chapter 9 of the USB
specification.
To initiate the data stage of the setup transaction
(for example, get the data for the GET DEVICE
DESCRIPTOR command), set up a buffer in
memory to store the received data.
Initialize the current (EVEN or ODD) RX or TX
(RX for IN, TX for OUT) EP0 BD to transfer the
data.
a)
b)
Write the Token register with the appropriate IN
or OUT token to Endpoint 0, the target device’s
default control pipe) for example, an IN token for
a GET
(U1TOK = 0x90). This will initiate an IN token on
the bus followed by a data packet from the
device to the host. When the data packet com-
to a Connected Device
Set the BD status (BD0STAT) to 0x8008 –
UOWN bit set, byte count of 8.
Set the BD data buffer address (BD0ADR)
to the starting address of the 8-byte
memory buffer containing the command, if it
is not already initialized.
Set the BD status (BD0STAT) UOWN bit to
‘1’, data toggle (DTS) to DATA1 and byte
count to the length of the data buffer.
Set the BD data buffer address (BD0ADR)
to the starting address of the data buffer if it
is not already initialized.
DEVICE
DESCRIPTOR command
Preliminary
9.
10. Initialize the current (EVEN or ODD) TX EP0 BD
11. Write the Token register with the appropriate IN
Note:
pletes, the BD0STAT is written and a transfer
done interrupt will be asserted (U1IR<TRNIF>).
For control transfers with a single packet data
phase, this completes the data phase of the
setup transaction. If more data needs to be
transferred, return to step 8.
To initiate the status stage of the setup transac-
tion, set up a buffer in memory to receive or send
the zero length status phase data packet.
to transfer the status data.
a)
b)
or OUT token to Endpoint 0, the target device’s
default control pipe) for example, an OUT token
for a GET DEVICE DESCRIPTOR command
(U1TOK = 0x10). This will initiate a token on the
bus, followed by a zero length data packet from
the host to the device. When the data packet
completes, the BD is updated with the hand-
shake from the device, and a transfer done inter-
rupt will be asserted (U1IR<TRNIF>). This
completes the status phase of the setup
transaction.
PIC32MX3XX/4XX
Set the BD status (BD0STAT) to 0x8000 –
UOWN bit to ‘1’, data toggle (DTS) to
DATA0 and byte count to ‘0’.
Set the BDT buffer address field to the start
address of the data buffer.
Some
respond to one transaction per frame.
devices
can
DS61143C-page 293
only
effectively