PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 453

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.3.4
To perform a write onto the parallel port, the user
writes to the PMDIN register (same register used for a
read operation). This causes the module to first acti-
vate the Chip Select lines and the address bus. The
write data from the PMDIN register is placed onto the
PMD data bus and the write line PMPWR is strobed.
20.3.5
In addition to the PMP interrupt, a BUSY bit is
provided to indicate the status of the module. This bit
is only used in Master modes.
While any read or write operation is in progress, the
BUSY bit is set for all but the very last peripheral bus
cycle of the operation. While the bit is set, any request
by the user to initiate a new operation will be ignored
(i.e., writing or reading the PMDIN register will not initi-
ate either a read nor a write).
EXAMPLE 20-2:
In most applications, the PMP’s Chip Select pin(s) pro-
vide the Chip Select interface and are under the timing
control of the PMP module. However, some applica-
tions may require the PMP Chip Select pin(s) not be
configured as a Chip Select, but as a high-order
address line, such as PMA<14> or PMA<15>. In this
situation, the application’s Chip Select function must be
provided by an available I/O port pin under software
control. In these cases, it is especially important that
the user’s software poll the BUSY bit to ensure any
read or write operation is complete before de-asserting
the software controlled Chip Select.
The following example illustrates a common technique.
© 2008 Microchip Technology Inc.
/*An generic C example PMP write function
*/
pmpWrite(unsigned int value)
{
}
/*An MPLAB C32 example PMP write function
*/
pmpWrite(unsigned int value)
{
}
utilizing the BUSY bit.
utilizing BUSY bit.
while(PMMODE & 0x8000);
PMDIN = value;
while(PMMODEbits.BUSY); // PMP busy?
PMDIN = value;
WRITE OPERATION
PARALLEL MASTER PORT STATUS
POLLING THE BUSY FLAG
// perform write
// perform write
// PMP busy?
Preliminary
If a large number of wait-states are used, or if the
PBCLK clock is operating slower than the SYSCLK
clock, it is possible for the PMP module to be in the pro-
cess of completing a read or write operation when the
next CPU instruction is attempting to read or write the
PMP module. For this reason, it is highly recommended
that the PMP’s BUSY bit be checked prior to any read
or write operation and any user operation that modifies
the PMADDR address register. See the following code
example.
Note:
PIC32MX3XX/4XX
During any Master mode read or write
operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
(T
including Wait states.
PBCLK )
, before the end of the operation,
DS61143C-page 451