PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 323

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

To prevent possible spurious interrupts when configur-
ing change notice interrupts, the following steps are
recommended:
1.
2.
3.
4.
5.
6.
7.
8.
9.
EXAMPLE 12-1:
© 2008 Microchip Technology Inc.
/*
*/
Disable CPU interrupts.
Set desired CN I/O pin as input by setting corre-
sponding TRISx register bits = 1.
Note: If the I/O pin is shared with an analog
peripheral, it may be necessary to set the corre-
sponding AD1PCFG bit = 1 to ensure that the
I/O pin is a digital input.
Enable change notice module
ON (CNCON<15>) = 1.
Enable individual CN input pin(s); enable
optional pull-up(s).
Read corresponding PORT registers to clear
mismatch condition on CN input pins.
Configure the CN interrupt priority, CNIP<2:0>,
and subpriority CNIS<1:0>.
Clear CN interrupt flag, CNIF = 0.
Enable CN interrupt enable, CNIE = 1.
Enable CPU interrupts.
The following code example illustrates a Change Notice
interrupt configuration for pins CN1(PORTC), CN4(PORTB) and CN18(PORTF).
unsigned int value;
/* NOTE: disable vector interrupts prior to configuration */
CNCON = 0x8000;
CNEN=
CNPUE= 0x00040012;
/* read port(s) to clear mismatch on change notice pins */
value = PORTB;
value = PORTC;
value = PORTF;
IPS6SET = 0x00140000; // Set priority level=5
IPS6SET = 0x00030000; // Set subpriority level=3
IFS1CLR
IEC1SET
/* re-enable vector interrupts after configuration */
0x00040012;
= 0x0001;
= 0x0001;
CN CONFIGURATION AND INTERRUPT INITIALIZATION EXAMPLE CODE
// Enable Change Notice module
// Enable CN1, CN4 and CN18 pins
// Enable weak pull ups for CN1, CN4 and CN18 pins
// Could have also done this in single
// operation by assigning IPS6SET = 0x00170000
// Clear the interrupt flag status bit
// Enable Change Notice interrupts
Preliminary
The port must be read first to clear the mismatch con-
dition, then the CN interrupt flag, CNIF (IFS1<0>), can
be cleared in software. Failing to read the port before
attempting to clear the CNIF bit may not allow the CNIF
bit to be cleared.
In addition to enabling the CN interrupt, an Interrupt
Service Routine (ISR), is required. Example 12-1 and
Example 12-2 show a partial code example of an ISR.
Note:
PIC32MX3XX/4XX
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143C - page 321