PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
10.9
The CRC Append mode is enabled by setting
CRCAPP (DCRCCON<6>).
In this mode, the behavior of the DMA channel is
changed.
Data read from the source will be fed into the CRC
generation module. No data is written to the destina-
tion address in CRC Append mode until a block trans-
fer completes or a pattern match occurs. On
completion, the CRC value will be written to the
address given by the Destination register (DCHxDSA).
This mode can be used for the CRC calculation of a
memory buffer, without actually performing a DMA
transfer to a destination.
CRC Append mode Features:
• Only the source is considered when deciding if a
• The destination address (DCHxDSA) is only used
• The destination size (DCHxDSIZ) can have a
• No CRC written back on an abort IRQ, user abort,
DS61143C-page 236
block transfer is complete.
as the location to write the generated CRC to.
maximum size of 4.
- If DCHxDSIZ is greater than 4, only 4 bytes are
- If DCHxDSIZ is less than 4, only DCHxDSIZ bytes
- The high bytes (bits 31:16) are written as 0’s if
- PLEN (CRCCON<11:8>) has no effect on the
bus error, etc.
written at the end of the transfer.
of the CRC are written to the destination address.
more than 16 bits of the CRC are written.
number of CRC bits that will be written to the
Destination register.
CRC Append Mode
Preliminary
10.9.1
Microchip recommends taking the following steps to
configure a CRC calculation in Background mode:
• Seed the CRC generator by writing the initial seed
• Set the polynomial generator by writing to the
• Set the polynomial generator length by writing the
• Attach the CRC calculation to the desired DMA
• Use the Append mode by setting the CRCAPP
• Enable the CRC calculation by setting the
• Program the DMA transfer destination with the
• Once the DMA transfer begins, the CRC
• Once the DMA transfer ends, the CRC result will
Refer to Example 10-5.
to the DCRCDATA register.
DCRCXOR register.
PLEN (DCRCCON<11:8>).
channel performing the transfer by writing the
CRCCH (DCRCCON<2:0>).
(DCRCCON<6>) bit.
CRCEN (DCRCCON<7>).
physical address of a variable where the CRC is
to be stored.
calculation will begin as well.
be deposited at the programmed DMA destination
address.
Note:
CRC APPEND MODE
CONFIGURATION
The configuration steps specific for the
CRC configuration are shown. The DMA
transfer configuration is the same as
previously explained (see Section 10.2
“DMA Controller Operation”).
© 2008 Microchip Technology Inc.