PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 451

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.3
A PMP Master mode cycle time is defined as the num-
ber of PBCLK cycles required by the PMP to perform a
read or write operation and is dependent on PBCLK
clock speed, PMP address/data multiplexing modes
and the number of PMP wait states, if any. Refer to the
PIC32MX Family Reference Manual, PMP Chapter, for
various timing diagrams. For specific setup and hold
timing characteristics, refer to Section 30.2 “AC Char-
acteristics and Timing Parameters” in this data
sheet.
A PMP master mode read or write cycle is initiated by
accessing (reading or writing) the PMDIN register. Sec-
tion TABLE 20-7: “PMP Read/Write Cycle Times”
below provides a summary of read and write PMP cycle
times for each multiplex configuration.
TABLE 20-7:
20.3.1
The Master mode configuration is determined primarily
by the interface requirements to the external device.
Address multiplexing, control signal polarity, data width
and Wait states typically dictate the specific configura-
tion of the PMP master port.
The following illustrates example settings for Master
Mode 2 operation:
• Select Master Mode 2 -
• Select 16-Bit Data mode -
• Select partial multiplexed addressing -
• Select auto-address increment -
• Enable Interrupt Request mode -
• Enable PMRD strobe -
• Enable PMWR strobe -
• Enable PMCS2 and PMCS1 Chip Selects -
• Select PMRD “active-low” pin polarity -
© 2008 Microchip Technology Inc.
Note:
MODE16 (PMMODE<10>) = 1.
ADRMUX<1:0> (PMCON<12:11>) = 01.
INCM<1:0> (PMMODE<12:11>) = 01.
IRQM<1:0> (PMMODE<14:13>) = 01.
MODE<1:0> (PMMODE<9:8>) = 10.
PTRDEN (PMCON<8>) = 1.
PTWREN (PMCON<9>) = 1.
CSF (PMCON<7:6>) = 10.
RDSP (PMCON<0>) = 0.
Master Mode Timing
Address/Data Multiplex Configuration
Wait states are not enabled
MASTER PORT CONFIGURATION
Full Multiplexed (16-bit data)
Full Multiplexed (8-bit data)
PMP READ/WRITE CYCLE TIMES
Partial Multiplex
Demultiplexed
Preliminary
The actual data rate of the PMP (the rate which user’s
code can perform a sequence of read or write opera-
tions) will be highly dependent on several factors:
• a user's application code content
• code optimization level
• internal bus activity
• other factors relating to the instruction execution
• Select PMWR “active-low” pin polarity -
• Select PMCS2, PMCS1 “active-low” pin polarity -
• Select 1 wait cycle for data setup -
• Select 2 wait cycles to extend PMRD/PMWR -
• Select 1 wait cycle for data hold -
• Enable upper 8 PMA<15:8> address pins -
ADRMUX bit
speed.
(PMCON<3>) = 0.
WAITB<1:0>(PMMODE<7:6>) = 00.
WAITM<3:0>(PMMODE<5:2>) = 01.
WAITB<1:0>(PMMODE<1:0>) = 00.
PMAEN<15:8> = 1 (lower 8 can be used as
general purpose I/O).
Note:
WRSP (PMCON<1>) = 0.
CS2P (PMCON<4>) = 0 and CS1P
settings
00
01
10
11
PIC32MX3XX/4XX
During any Master mode read or write
operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
(T
including Wait states. The user’s applica-
tion must check the status of the busy flag
to ensure it is = 0 before initiating the next
PMP operation.
PBCLK )
, before the end of the operation,
Read
2
5
8
5
PMP Cycle Time
(PBCLK cycles)
DS61143C-page 449
Write
3
6
9
6