PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 334

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
13.5
Timer1 can generate an interrupt on a period match
event or a gate event, caused by the falling edge of the
external gate signal.
Timer1 sets the interrupt flag bit, T1IF (IFS0<4>),
whenever a Timer1 event is generated. Refer to a spe-
cific Timer mode for details regarding event conditions.
When a Timer1 event is generated, the interrupt flag bit
is set within 1 PBCLK + 2 SYSCLK cycles. If Timer1
Interrupt Enable bit is set, T1IE (IEC0<4>) = 1, an
interrupt is generated.
The Timer1 module is enabled as a source of interrupts
through its respective interrupt enable bit, T1IE
(IEC0<4>). The Timer1 Interrupt Flag, T1IF (IFS0<4>),
must be cleared in software.
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• T1IP<2:0> (IPC1<4:2>)
• T1IS<1:0> (IPC1<1:0)
Setting Timer1 interrupt priority level = 0 effectively
disables the timer’s ability to generate an interrupt.
In addition to enabling the Timer1 interrupt, an Interrupt
Service Routine, ISR, is generally required. Below is a
partial code example of an ISR.
EXAMPLE 13-5:
EXAMPLE 13-6:
DS61143C-page 332
void __ISR(TIMER_1_VECTOR, IPL3) T1_Interrupt_ISR(void)
{
}
Note:
Note:
T1CON = 0x0
TMR1 = 0x0;
PR1 = 0xFFFF;
IPC1SET = 0x000C;
IPC1SET = 0x0001;
IFS0CLR = 0x0010;
IEC0SET = 0x0010;
T1CONSET = 0x8000;
... perform application specific operations in response to the interrupt
IFS0CLR
Timer Interrupts
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
The timer ISR code example shows MPLAB
manual regarding support for ISRs.
= 0x0010;
TIMER INTERRUPT AND PRIORITIES
TIMER ISR
// Set prescaler at 1:1, internal clock source
// Clear timer register
// Load period register
// Set priority level=3
// Set subpriority level=1
// Could have also done this in single
// operation by assigning IPC1SET = 0x000D
// Clear Timer interrupt status flag
// Enable Timer interrupts
// Start Timer
// Be sure to clear the Timer 1 interrupt status
// Stop the Timer and Reset Control register
Preliminary
®
C32 C Compiler specific syntax. Refer to your compiler
© 2008 Microchip Technology Inc.