PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 294

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
11.31 Enabling Host Mode and
To enable Host mode, perform the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
11.31.1
When acting as a host, a transaction consists of the fol-
lowing:
1.
2.
3.
4.
DS61143C-page 292
Enable Host mode (U1CON<HOSTEN> = 1).
This enables the D+ and D- pull-down resistors,
and disables the D+ and D- pull-up resistors. To
reduce noise on the bus, disable the SOF
packet generation by writing the SOF Enable bit
to ‘0’ (U1CON<SOFEN> = 0).
Enable
(U1IE<ATTACHIE> = 1).
Wait
(U1IR<ATTACHIF>).
This is signaled by the USB device changing the
state of D+ or D- from ‘0’ to ‘1’ (SE0 to JSTATE).
After it occurs, wait for the device power to sta-
bilize (10 ms is minimum, 100 ms is recom-
mended).
Check the state of the JSTATE and SE0 bits in
the control register U1CON.
If U1CON<JSTATE> is ‘0’, the connecting
device is low speed; otherwise, the device is full
speed.
If the connecting device is low speed, set the
low-speed enable bit in the address register
(U1ADDR<LSPDEN>= 1), and the low-speed
bit
(U1EP0<LSPD> = 1). But, if the device is full
speed, clear these bits.
Reset the USB device by sending the Reset sig-
naling for at least 50 ms (U1CON<USBRST> =
1).
(U1CON<USBRST> = 0).
Enable SOF packet generation to keep the con-
nected
(U1CON<SOFEN> = 1).
Wait 10 ms for the device to recover from Reset.
Perform enumeration as described in Chapter 9
of the USB 2.0 specification.
Software configures the appropriate BD (End-
point n, DIR, PPBI), and sets the UOWN bit to ‘1’
(HW owned).
Software checks the state of TOKBUSY
(U1CON<5>) to verify that any previous
transaction has completed.
Software writes the address of the target device
in the U1ADDR register.
Software writes the endpoint number and the
desired TOKEN PID (IN, OUT, or SETUP) to the
U1TOK register.
Discovering a Connected Device
in
After
HOST TRANSACTIONS
for
device
the
the
50
the
Endpoint
ms,
from
device
device
terminate
going
0
attach
attach
Control
into
the
suspend
interrupt
interrupt
register
Reset
Preliminary
5.
6.
7.
8.
9.
10. Hardware updates the BD, and writes the
11. Hardware updates the U1STAT register, and
12. Hardware reads the next BD (EVEN or ODD) to
13. Software should read the U1STAT register, and
If Software does not set the UOWN bit to ‘1’ in the
appropriate BD prior to writing the U1TOK register, the
module will read the descriptor and do nothing.
Hardware reads the BD to determine the appro-
priate action, and to obtain the pointer to data
memory.
Hardware issues the correct TOKEN PID (IN,
OUT, SETUP) on the USB link.
If the transaction is a transmit transaction (OUT,
SETUP), the USB module reads the packet data
out of data memory. Then the module follows
with the desired DATA PID (DATA0/DATA1) and
packet data.
If the transaction is a receive transaction (IN),
the USB module waits to receive the DATA PID
and packet data. Hardware writes the packet
data to memory.
Hardware issues or waits for a Handshake PID
(ACK, NAK, or STALL), unless the endpoint is
set up as an isochronous endpoint (EPHSHK bit
U1EPx<0> is cleared).
UOWN bit to ‘0’ (SW owned).
sets the TRNIF (U1IR<3>) interrupt.
see whether it is owned by the USB module. If it
is, hardware begins the next transaction.
then clear the TRNIF interrupt.
© 2008 Microchip Technology Inc.