MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 122

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
The need to move large amounts of data quickly can limit throughput in DSP engines.
However, data can be moved efficiently by using the MOVEM instruction, which
automatically generates line-sized burst references and is ideal for filling registers quickly
with input data, filter coefficients, and output data. Loading an operand from memory into
a register during a MAC operation makes some DSP operations, especially filtering and
convolution, more manageable.
The MACSR has a 4-bit operational mode field and three condition flags. The operational
mode bits control the overflow/saturation mode, whether operands are signed or unsigned,
whether operands are treated as integers or fractions, and how rounding is performed.
Negative, zero and overflow flags are also provided.
The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask
register (MASK), and MACSR, are described in Section 3.1.0.1, “MAC Programming
Model.”
3.1.0.3 MAC Instruction Set Summary
The MAC unit supports the integer multiply operations defined by the baseline ColdFire
architecture, as well as the new multiply-accumulate instructions. Table 3-1 summarizes
the MAC unit instruction set.
Multiply Signed
Multiply Unsigned
Multiply Accumulate
Multiply Accumulate
with Load
Load Accumulator
Store Accumulator
Load MACSR
Store MACSR
Store MACSR to CCR
Load MASK
Store MASK
3.1.0.4 Data Representation
The MAC unit supports three basic operand types:
3-4
• Two’s complement signed integer: In this format, an N-bit operand represents a
Instruction
number within the range -2
of the least significant bit.
MULS <ea>y,Dx
MULU <ea>y,Dx
MAC Ry,RxSF
MSAC Ry,RxSF
MAC Ry,RxSF,Rw
MSAC Ry,RxSF,Rw
MOV.L {Ry,#imm},ACC
MOV.L ACC,Rx
MOV.L {Ry,#imm},MACSR Writes a value to the MACSR
MOV.L MACSR,Rx
MOV.L MACSR,CCR
MOV.L {Ry,#imm},MASK
MOV.L MASK,Rx
Table 3-1. MAC Instruction Summary
Mnemonic
(N-1)
MCF5407 User’s Manual
< operand < 2
Multiplies two signed operands yielding a signed result
Multiplies two unsigned operands yielding an unsigned result
Multiplies two operands, then adds or subtracts the product
to/from the accumulator
Multiplies two operands, then adds or subtracts the product
to/from the accumulator while loading a register with the
memory operand
Loads the accumulator with a 32-bit operand
Writes the contents of the accumulator to a register
Write the contents of MACSR to a register
Write the contents of MACSR to the processor’s CCR register
Writes a value to MASK
Writes the contents of MASK to a register
(N-1)
- 1. The binary point is to the right
Description