MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 266

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chip-Select Registers
10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7)
Each chip-select control register, Figure 10-4, controls the auto acknowledge, external
master support, port size, burst capability, and activation of each chip select. Note that to
support the global chip select, CS0, the CSCR0 reset values differ from the other CSCRs.
CS0 allows address decoding for boot ROM before system initialization.
Table 10-10 describes CSCRn fields.
Reset: Other CSCRs
15–14
13–10
10-8
Bits
Bits
5–1
9
0
Reset: CSCR0
Name
WS
Name
—
—
SC,
UC,
C/I,
SD,
UD
V
Address
Figure 10-4. Chip-Select Control Registers (CSCR0–CSCR7)
Field
R/W
Reserved, should be cleared.
Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by
the external system regardless of the number of wait states generated. In that case, the external
transfer acknowledge ends the cycle. An external TA supersedes the generation of an internal TA.
Reserved, should be cleared.
Address space mask bits. These bits determine whether the specified accesses can occur to the
address space defined by the BAM for this chip select.
C/I
SC Supervisor code address space mask
SD Supervisor data address space mask
UC User code address space mask
UD User data address space mask
0 The address space assigned to this chip select. is available to the specified access type.
1 The address space assigned to this chip select. is not available (masked) to the specified access
Note that if if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on external
master or DMA access.
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip
select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
type. If this address space is accessed, chip select is not activated and a regular external bus
cycle occurs.
Table 10-9. CSMRn Field Descriptions (Continued)
15
CPU space and interrupt acknowledge cycle mask
—
—
14
Table 10-10. CSCRn Field Descriptions
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6); 0x0DE (CSCR7)
13
0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
11_11
WS
MCF5407 User’s Manual
10
—
—
9
Description
Description
AA PS1 PS0 BEM BSTR BSTW
D7
Unitialized
8
R/W
D6
7
D5
6
D3
5
4
3
—
2
—
0