MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 166

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
5.4.1 Address Attribute Trigger Registers (AATR, AATR1)
The address attribute trigger registers (AATR, AATR1) define address attributes and a mask
to be matched in the trigger. The register value is compared with address attribute signals
from the processor’s local high-speed bus, as defined by the setting of the trigger definition
register (TDR) for AATR and the extended trigger definition register (XTDR) for AATR1.
5-10
0x0A–0x0B Reserved
0x10–0x15 Reserved
DRc[4–0]
0x0C
0x0D
0x1C
0x1D
0x0E
0x0F
0x1A
0x1B
0x1E
0x1F
0x07
0x08
0x09
0x16
0x17
0x18
0x19
Debug control registers can be written by the external
development system or the CPU through the WDEBUG
instruction.
CSR is write-only from the programming model as debug
control register 0x00 using the supervisor-mode WDEBUG
instruction. It can be read from and written through the BDM
port using the
Trigger definition register
Program counter breakpoint register
Program counter breakpoint mask register
Address breakpoint high register
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
Address attribute trigger register 1
Extended trigger definition register
Program counter breakpoint 1 register
Reserved
Program counter breakpoint register 2
Program counter breakpoint register 3
Address high breakpoint register 1
Address low breakpoint register 1
Data breakpoint register 1
Data breakpoint mask register 1
Table 5-6. BDM/Breakpoint Registers (Continued)
Register Name
RDMREG
MCF5407 User’s Manual
and
NOTE:
WDMREG
commands.
Abbreviation
DBMR1
ABHR1
ABLR1
AATR1
PBMR
DBMR
ABHR
XTDR
DBR1
ABLR
PBR1
PBR2
PBR3
DBR
TDR
PBR
—
—
—
0x0000_0000
0x0000_0005
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Initial State
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p. 5-18
p. 5-16
p. 5-16
p. 5-12
p. 5-12
p. 5-15
p. 5-15
p. 5-10
p. 5-19
p. 5-16
p. 5-16
p. 5-16
p. 5-12
p. 5-12
p. 5-15
p. 5-15
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