MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 514

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision C Debug
A.8.2 On-Chip Breakpoint Registers
The Debug B core debug module included three basic types of on-chip breakpoint registers:
The mask registers can be used to “don’t care” the equivalent bits in the breakpoint
registers.
Additions to the breakpoint implementation are as follows:
The addition of these new breakpoint registers also requires the appropriate control and
configuration functions be added to the debug programming model. The affected BDM
command and new register formats are described below. The revised BDM command is
write debug module register (
A.8.2.1 Write Debug Module Register (
The operand (longword) data is written to the specified debug module register. All 32 bits
of the register are altered by the write operation. The debug module’s programming model
can be accessed either from the serial BDM communication channel or from the processor’s
execution of the supervisor-mode WDEBUG instruction. DSCLK must be inactive while
WDEBUG executes.
Figure A-5 defines the operand data format.
A-12
15
• A 32-bit PC breakpoint register and a 32-bit PC breakpoint mask
• Two 32-bit address registers, which can be used to specify a single address or a range
• A 32-bit data breakpoint register and a 32-bit data breakpoint mask
• Three more 32-bit PC breakpoint registers
• Two more 32-bit address registers (ABLR1, ABHR1) plus an attribute register
• One more 32-bit data breakpoint register and a 32-bit data breakpoint mask
of addresses
(AATR1) and mask register, which can be used to specify a single address or a range
of addresses
14
0x2
Figure A-5. Write Debug Module Register Command (
13
12
11
WDMREG
10
0xC
MCF5407 User’s Manual
9
).
D[31:16]
8
D[15:0]
7
WDMREG
0x4
6
5
)
4
3
WDMREG
DRc
2
)
1
0