MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 123

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2 MAC Instruction
Table 3-2 shows standard timings for two-operand MAC instructions.
Table 3-3 shows standard timings for MAC move instructions.
Opcode
msac.w
msac.w
mulu.w
muls.w
mac.w
msac.l
mac.w
msac.l
muls.l
mulu.l
mac.l
mac.l
• Two’s complement unsigned integer: In this format, an N-bit operand represents a
• Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit.
number within the range 0 < operand < 2
least significant bit.
The remaining bits signify the first N-1 bits after the binary point. Given an N-bit
number, a
This format can represent numbers in the range -1 < operand < 1 - 2
For words and longwords, the greatest negative number that can be represented is -1,
whose internal representation is 0x8000 and 0x0x8000_0000, respectively. The
most positive word is 0x7FFF or (1 - 2
0x7FFF_FFFF or (1 - 2
Ry,Rx,ea,Rw
Ry,Rx,ea,Rw
Ry,Rx,ea,Rw
Ry,Rx,ea,Rw
<ea>,Dx
<ea>,Dx
<ea>,Dx
<ea>,Dx
Ry,Rx
Ry,Rx
Ry,Rx
Ry,Rx
<ea>
Table 3-2. Two-Operand MAC Instruction Execution Times
N-1
+
a
Chapter 3. Hardware Multiply/Accumulate (MAC) Unit
N 2
N-2
i
∑
=
1(0/0)
3(0/0)
1(0/0)
3(0/0)
3(0/0)
3(0/0)
5(0/0)
5(0/0)
–
Rn
a
—
—
—
—
0
N-3
2
(
... a
i
+
-31
1(1/0)
3(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
(An)
—
—
—
—
1 N
2
).
a
–
1
a
Execution Timings
0
)
(An)+
1(1/0)
3(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
, its value is given by the following formula:
⋅
—
—
—
—
ai
1(1/0)
3(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
-(An)
-15
—
—
—
—
N
); the most positive longword is
Effective Address
- 1. The binary point is to the right of the
(d16,An) (d8,An,Xi*SF)
1(1/0)
3(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
—
—
—
—
MAC Instruction Execution Timings
4(1/0)
4(1/0)
—
—
—
—
—
—
—
—
—
—
(xxx).wl
3(1/0)
3(1/0)
(N-1)
—
—
—
—
—
—
—
—
—
—
.
#<xxx>
3(0/0)
3(0/0)
—
—
—
—
—
—
—
—
—
—
3-5