MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 409

IC MPU 32B 220MHZ COLDF 208-FQFP

MCF5407AI220

Manufacturer Part Number
MCF5407AI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Datasheets

Specifications of MCF5407AI220

Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
220 MHz
Operating Supply Voltage
1.8 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Program Memory Size
24KB
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Address
Data
Read/Write
Size
Transfer start
Address strobe
Transfer acknowledge
Transfer in progress
Transfer type
Transfer modifier
Interrupt request
Bus request
Bus grant
Bus driven
Reset in
Clock input
Bus clock out
Reset out
Auto-acknowledge
configuration
Port size configuration
Signal Name
2
2
A[31:0]
D[31:0]
R/W
SIZ[1:0]
TS
AS
TA
TIP/PP7
TT[1:0]
TM[2:0]
IRQ7, IRQ5,
IRQ3, IRQ1
BR
BG
BD
RSTI
CLKIN
BCLKO
RSTO
AA_CONFIG
PS_CONFIG[1:0] Controls port size for CS0 at reset
Abbreviation
Section 17.3, “Interrupt Control Signals”
Section 17.5, “Clock and Reset Signals”
Table 17-1. MCF5407 Signal Index
Section 17.4, “Bus Arbitration Signals”
Section 17.2, “MCF5407 Bus Signals”
Chapter 17. Signal Descriptions
32-bit address bus. A[4:2] indicate
the interrupt level for external
interrupts.
Data bus. D[7:0] are loaded at reset
for bus configuration.
Identifies read and write transfers
Indicates the data transfer size
Indicates the start of a bus transfer
Indicates a bus cycle has been
initiated and address is stable
Assertion terminates transfer
synchronously
Indicates a bus cycle is in progress;
multiplexed with PP7
Indicates transfer type: normal, CPU
space, emulator mode, or DMA;
multiplexed with PP[1:0]
Provides transfer modifier
information; multiplexed with
TM2/PP4 and
TM[1:0]/PP[3:2]/DACK[1:0]
Four external interrupts are set to
default levels 1,3,5,7; user-alterable.
Indicates processor needs bus
Arbiter asserts to grant mastership.
Indicates processor is driving bus
Processor reset input
Input used to clock internal logic
Bus clock reference output
Processor reset output
Controls auto acknowledge timing
for CS0 at reset
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
Parallel
Parallel
Parallel
Reset
Three
Three
Three
Three
Three
Three
Three
state
state
state
state
state
state
state
High
High
port
port
port
Low
User cfg 17-14
Pull-Up Page
Note
Up
Up
Up
Up
Up
Overview
1
17-10
17-10
17-10
17-12
17-12
17-12
17-12
17-12
17-13
17-13
17-13
17-13
17-13
17-13
17-14
17-7
17-7
17-8
17-8
17-8
17-9
17-9
17-9
17-3

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