MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 170

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
Table 5-11 describes CSR fields.
5-14
31–28
23–20
Bit
27
26
25
24
19
18
17
16
15
14
13
BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also
FOF
TRG
HALT
BKPT
HRL
—
BKD
PCD
IPW
MAP
TRC
EMU
Name
output on PSTDDATA when it is not displaying PST or other processor data. BSTAT is cleared by a
TDR or XTDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM.
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and
forced entry into BDM. Reset and the debug
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset
and the debug
Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset and
the debug
Hardware revision level. Indicates the level of debug module functionality. An emulator could use
this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A)
0001 Revision B
0010 Revision C (this is the only valid value for the MCF5407)
Reserved, should be cleared.
Breakpoint disable. Used to disable the normal BKPT input functionality and to allow the assertion
of BKPT to generate a debug interrupt.
0 Normal operation
1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor.
PSTCLK disable. Setting PCD disables generation of PSTCLK and PSTDDATA outputs and forces
them to remain quiescent.
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s
programming model registers. IPW can be modified only by commands from the external
development system.
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a
trace exception occurs.
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 5.6.1.1, “Emulator Mode.”
The processor makes this interrupt request pending until the next sample point, when the
exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per
instruction. There is no support for nesting debug interrupts.
TM = 101 or 110.
GO
command clears this bit.
Table 5-11. CSR Field Descriptions
GO
command reset HALT.
MCF5407 User’s Manual
Description
GO
command clear TRG.