MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 173

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

program counter register when the appropriate valid bit is set and TDR and/or XTDR are
configured appropriately. PBR bits are masked by clearing corresponding PBMR bits.
Results are compared with the processor’s program counter register, as defined in TDR
and/or XTDR. PBR1–PBR3 are not masked. Figure 5-11 shows the PC breakpoint register.
1
Table 5-15 describes PBR, PBR1, PBR2, and PBR3 fields.
PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
instruction and via the BDM port using the
Table 5-16 describes PBMR fields.
DRc[4–0]
31–0 Mask
31–1 Address PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger.
0
Bits
PBR does not have a valid bit. PBR[0] is read as 0 and should be cleared.
Bits
DRc[4–0]
Figure 5-11. Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3)
Reset
Field
R/W Write. PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and
Reset
Field
R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
V
Name
Name
through the BDM port using the
“Command Set Descriptions.”
31
instruction and via the BDM port using the wdmreg command.
Figure 5-12. Program Counter Breakpoint Mask Register (PBMR)
31
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to
the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
PBR does not have a valid bit.
Valid. Breakpoint registers are compared with the processor’s program counter register when the
appropriate valid bit is set and TDR and/or XTDR are configured appropriately. This bit is not
implemented on PBR.
Table 5-15. PBR, PBR1, PBR2, PBR3 Field Descriptions
Table 5-16. PBMR Field Descriptions
0x08 (PBR); 0x18 (PBR1); 0x1A (PBR2); 0x1B (PBR3)
RDMREG
Chapter 5. Debug Support
and
Program Counter
WDMREG
WDMREG
Mask
—
—
Description
Description
0x09
commands using values shown in Section 5.5.3.3,
command. Figure 5-12 shows PBMR.
Programming Model
1
1
—
—
5-17
0
V
0
0
1