MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 494

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
I
20.7 I
Table 20-11 lists specifications for the I
Table 20-12 lists specifications for the I
Figure 20-18.
I1
I2
I3
I4
I5
I6
I7
I8
I9
Figure 20-18 shows timing for the values in Table 20-11 and Table 20-12.
20-18
2
Num
C Input/Output Timing Specifications
1
1
Programming IFDR with the maximum frequency (IFDR = 0x20) results in the minimum output timings listed
here. The I
period. The actual position is affected by the prescale and division values programmed in IFDR.
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time
SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
Specified at a nominal 50-pF load.
2
1
3
1
1
1
1
I1
I2
I3
I4
I5
I6
I7
I8
I9
Num
Table 20-12. I
Start condition hold time
Clock low period
SCL/SDA rise time (V
Data hold time
SCL/SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Table 20-11. I
2
2
C interface is designed to scale the data transition time, moving it to the middle of the SCL low
Start condition hold time
Clock low period
SCL/SDA rise time (V
Data hold time
SCL/SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
C Input/Output Timing Specifications
2
2
C Output Timing Specifications between SCL and SDA
IH
C Input Timing Specifications between SCL and SDA
IL
= 2.4 V to V
= 0.5 V to V
IH
IL
Characteristic
= 2.4 V to V
= 0.5 V to V
Characteristic
IL
IH
MCF5407 User’s Manual
= 0.5 V)
= 2.4 V)
IL
IH
2
= 0.5 V)
= 2.4 V)
C input timing parameters shown in Figure 20-18.
2
C output timing parameters shown in
Note 2
54 MHz CLKIN
Min
54 MHz CLKIN
10
10
20
10
—
Min
6
7
2
—
—
2
8
0
4
0
2
2
Note 2
Max
Max
—
—
—
—
—
—
—
1
1
—
—
—
—
—
—
—
3
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Units
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
mS
mS
nS
nS
Units
nS