MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 359

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

mode, in modem mode the Tx FIFO in UART1 can be loaded while the Tx is disabled. For
UART1, FIFOs can be accessed as longwords.
Figure 14-15 shows the configuration of the UTB1. These bits contain the samples in the
transmitter buffer for UART1.
14.3.13 UART Input Port Change Registers (UIPCRn)
The input port change registers (UIPCRn), Figure 14-16, hold the current state and the
change-of-state for CTS.
Table 14-12 describes UIPCRn fields.
14.3.14 UART Auxiliary Control Register (UACRn)
The UART auxiliary control registers (UACRn), Figure 14-12, control the input enable.
Bits Name
7–5
3–1
Address
Address
4
0
Reset
Reset
Field
Field
R/W
R/W
COS
CTS
—
—
31
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition). Not used in modem mode.
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the CTS input. UACRn can be programmed to
Reserved, should be cleared.
Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS. If CTS is
detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. This
bit is not used in modem mode.
0 The current state of the CTS input is asserted.
1 The current state of the CTS input is negated.
7
generate an interrupt to the CPU when a change of state is detected.
Figure 14-16. UART Input Port Change Register (UIPCRn)
Figure 14-15. UART Transmitter Buffer for UART1 (UTB1)
TB[31:24]
—
Table 14-12. UIPCRn Field Descriptions
24
0000
23
0000_0000_0000_0000_0000_0000_0000_0000
MBAR + 0x1D0 (UIPCR0), 0x210 (UIPCR1)
Chapter 14. UART Modules
5
TB[23:16]
COS
MBAR + 0x20C
4
Write only
Read only
Description
16
15
0
3
TB[15:8]
111
8
11
7
Register Descriptions
1
TB[7:0]
CTS
CTS
0
14-17
0