HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 100

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.1
The SH microprocessor has an on-chip 16-bit multifunction timer pulse unit (MTU) with three
channels of 16-bit timers.
8.1.1
Note: * When channels 0 to 2 are set to PWM mode 1
Can process a maximum of six different pulse outputs and inputs.
Has eight timer general registers (TGR), four for channel 0 and two each for channels 1 and 2,
that can be set to function independently as output compare registers or (except for TGR0B
and TGR0D of channel 0) as input capture registers. The channel 0 TGRC and TGRD registers
can be used as buffer registers.
Can select six counter input clock sources for all channels
All channels can be set for the following operating modes:
Channel 0 can be set for buffer operation
Cascade connection operation
High speed access via internal 16-bit bus
Eleven interrupt sources
Compare match waveform output: 0 output/1 output/toggle output selectable.
Input capture function: Selectable rising edge, falling edge, or both rising and falling edge
Counter clearing function: Counters can be cleared by a compare-match or input capture.
Synchronizing mode: Two or more timer counters (TCNT) can be written to
PWM mode: PWM output can be provided with any duty cycle. When combined with the
Input capture register double buffer configuration possible
Output compare register automatic re-write possible
Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1
Channel 0 has two dual-function compare-match/input capture interrupts, two compare-
detection.
simultaneously. Two or more timer counters can be simultaneously cleared by a compare-
match or input capture. Counter synchronization functions enable synchronized register
input/output.
counter synchronizing function, enables up to four-phase* PWM output.
overflow/underflow
match interrupts, and one overflow interrupt, which can be requested independently.
Section 8 Multifunction Timer Pulse Unit (MTU)
Overview
Features
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