HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 234

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
Figure 12.10 shows an example of SCI receive operation in the multiprocessor format.
Receiving Multiprocessor Serial Data: Figure 12.11 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.
1. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.
2. SCI status check and compare to ID reception: Read the serial status register (SSR), check that
3. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
4. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data
224
Figure 12.10 SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE)
in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
bits in SSR to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
from the receive data register (RDR).
TDRE
TEND
Serial
data
interrupt
request
1
TxI
Start
bit
0
clears TDRE to 0
data in TDR and
handler writes
TxI interrupt
D0 D1
1 frame
Data
Multiprocessor
D7
and One Stop Bit)
0/1
interrupt
bit
request
TxI
Stop
bit
1
Start
bit
0
D0
D1
Data
Multiprocessor
D7 0/1
bit
interrupt
request
TEI
Stop
bit
1
(marking
state)
Idle
1