HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 196

MPU 5V 0K 100-QFP

HD6417011VX20V

Manufacturer Part Number
HD6417011VX20V
Description
MPU 5V 0K 100-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7010r
Datasheet

Specifications of HD6417011VX20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
POR, PWM
Number Of I /o
11
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417011VX20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.3.2
One of four clocks ( /8, /32, /128, /512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 11.3 shows the timing.
11.4
11.4.1
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details.
11.4.2
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 11.4 shows
the CMF bit set timing.
186
CMCNT input
Internal clock
CMCNT
CMCNT Count Timing
Interrupts
Interrupt Sources
Compare Match Flag Set Timing
clock
CK
N – 1
Figure 11.3 Count Timing
N
N + 1

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