HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 211

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 4: FER
0
1
Bit 3: PER
0
1
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error.
Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to
a parity error.
Description
Receiving is in progress or has ended normally (initial value). Clearing the RE bit
to 0 in the serial control register does not affect the FER bit, which retains its
previous value.
FER is cleared to 0 when the chip is power-on reset or software reads FER after
it has been set to 1, then writes 0 in FER
A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked to see if it is a 1. The second stop bit is not checked. When a
framing error occurs, the SCI transfers the receive data into the RDR but does
not set RDRF. Serial receiving cannot continue while FER is set to 1.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0
Description
Receiving is in progress or has ended normally (initial value). Clearing the RE bit
to 0 in the serial control register does not affect the PER bit, which retains its
previous value.
PER is cleared to 0 when the chip is power-on reset or software reads PER after
it has been set to 1, then writes 0 in PER
A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into the RDR but does not set RDRF. Serial receiving cannot
continue while PER is set to 1.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR)
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