HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 71

MPU 5V 0K 100-QFP

HD6417011VX20V

Manufacturer Part Number
HD6417011VX20V
Description
MPU 5V 0K 100-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7010r
Datasheet

Specifications of HD6417011VX20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
POR, PWM
Number Of I /o
11
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417011VX20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.2
There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules.
Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the
highest). Giving an interrupt a priority level of 0 masks it.
6.2.1
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by
edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either
the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15.
6.2.2
IRQ interrupts are requested by input from pins IRQ0–IRQ7. Set the IRQ sense select bits
(IRQ0S–IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge
detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt
priority registers A and B (IPRA–IPRB).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F–IRQ7F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request
detection results are maintained until the interrupt request is accepted. Confirmation that IRQ
interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F–IRQ7F) of the
IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection
results can be withdrawn.
In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt.
60
Interrupt Sources
NMI Interrupts
IRQ Interrupts

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