HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 209

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2: TEIE
0
1
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
12.2.7
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a power-on reset.
Note: The only value that can be written is a 0 to clear the flag.
Bit 7: TDRE
0
1
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bits 1 and 0—Reserved. These bits always read 0. The write value should always be 0.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the TDR into the TSR and new serial transmit data can be written in the TDR.
Initial value:
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
Serial Status Register (SSR)
R/W:
Bit:
Description
TDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE
TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when the chip is power-on reset the TE bit in the serial control
register (SCR) is cleared to 0, or TDR contents are loaded into TSR, so new data
can be written in TDR
R/(W)*
TDRE
7
1
Description
Transmit-end interrupt (TEI) requests are disabled* (initial value)
Transmit-end interrupt (TEI) requests are enabled.*
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
2
1
R
MPB
1
0
R
MPBT
R/W
0
0
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