HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 26

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.3
SH7011 CPU
BRA
ADD
Multiplication/Accumulation Operation: 16-bit
executed in one to two cycles. 16-bit 16-bit + 64-bit
operations are executed in two to three cycles. 32-bit
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4
SH7011 CPU
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Immediate Data: Byte (8 bit) immediate data resides in instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. An immediate
data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode
with displacement (table 2.5).
14
64-bit multiplication/accumulation operations are executed in two to four cycles.
TRGET
R1,R0
R1,R0
TRGET0
TRGET1
#1,R0
#0,R0
TRGET
Delayed Branch Instructions
T Bit
Description
T bit is set when R0 R1. The
program branches to TRGET0
when R0 R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD. T bit is
set when R0 = 0. The program
branches if R0 = 0.
Description
Executes an ADD before
branching to TRGET
16-bit
32-bit
64-bit multiplication/accumulation
32-bit multiplication operations are
Example of Conventional CPU
ADD.W
BRA
Example of Conventional CPU
CMP.W
BGE
BLT
SUB.W
BEQ
64-bit and 32-bit 32-bit + 64bit
R1,R0
TRGET0
TRGET1
#1,R0
TRGET
R1,R0
TRGET