HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 252

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.4.2
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or MTU trigger input,
A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH1 = 1).
When more than one channel has been selected, A/D conversion starts on the second channel
(AN1 or AN5) as soon as conversion ends on the first channel.
A/D conversion is performed repeatedly on all the selected channels until the ADST bit is cleared
to 0. The conversion results are transferred to and stored in the ADDR register for each channel.
To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0
before changing the mode or analog input channels. After the change is made, the first channel is
selected and A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change
and setting of the ADST bit can be carried out simultaneously).
An example of the A/D conversion operation in scan mode when three channels (AN0–AN2) in
group 0 are selected is described below. Figure 13.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), group 0 is selected as the scan group (CH2 = 0), analog
2. A/D conversion starts on the first channel (AN0), and when completed, the result is transferred
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion is completed for all the selected channels (AN0–AN2), ADF is set to 1, the
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
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input channels AN0-AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started
(ADST = 1).
to ADDRA. Next, conversion of the second channel (AN1) starts automatically.
first channel (AN0) is selected again, and conversion is performed on that channel. If the ADIE
bit is also 1, an ADI interrupt is requested when conversion is completed.
cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts
again from the first channel (AN0).
Scan Mode (SCAN = 1)