HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 24

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.2
2.2.1
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure
2.4).
2.2.2
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if you try to access word data starting from an
address other than 2n or longword data starting from an address other than 4n. In such cases, the
data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack
pointer (SP, R15), uses only longword data starting from address 4n because this area holds the
program counter and status register (figure 2.5).
2.2.3
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
12
Data Formats
Data Format in Registers
Data Format in Memory
Immediate Data Format
Address 2n
Address 4n
Figure 2.5 Byte, Word, and Longword Alignment
31
Figure 2.4 Longword Operand
Address m
31
Byte
Address m + 1
Word
Longword
23
Byte
Longword
Address m + 2
15
Byte
Address m + 3
Word
7
Byte
0
0