HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 124

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit n: CSTn
0
1
Note: n = 2 to 0.
8.2.9
The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or
synchronous TCNT counter operation for channels 0–2. Channels for which 1 is set in the
corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset.
Bits 7–3—Reserved. These bits always read 0. The write value should always be 0.
Bits 2–0—Timer Synchronization 2–0 (SYNC2–SYNC0): Selects operation independent of, or
synchronized to, other channels. Synchronous operation allows synchronous clears due to
multiple TCNT synchronous presets and other channel counter clears. A minimum of two
channels must have SYNC bits set to 1 for synchronous operation. For synchronization
clearing, it is necessary to set the TCNT counter clear sources (the CCLR2–CCLR0 bits of the
TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel
correspondence are indicated in the tables below.
SYNC2: Channel 2 (TCNT2)
SYNC1: Channel 1 (TCNT1)
SYNC0: Channel 0 (TCNT0)
Initial value:
If 0 is written to a CST bit during operation with the TIOC pin in the output state, the counter
stops, but the TIOC pin output compare output level is maintained. If a write is performed on
the TIOR register while a CST bit is 0, the pin output level is updated to the set initial output
value.
Timer Synchro Register (TSYR)
R/W:
Bit:
—
7
0
R
Description
TCNTn count is halted (initial value)
TCNTn counts
—
6
0
R
—
5
0
R
—
4
0
R
—
3
0
R
SYNC2
R/W
2
0
SYNC1 SYNC0
R/W
1
0
R/W
0
0
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