HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 239

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.5
The following points should be noted when using the SCI.
TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag
indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers
data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data
is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the
data has not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to
check that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 12.9 indicates the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR
contents cannot be transferred to the RDR, so receive data is lost.
Table 12.9 SSR Status Flags and Transfer of Receive Data
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity
error
Note: O = Receive data is transferred from RSR to RDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Receive Data Sampling Timing and Receive Margin: The SCI operates on a base clock of 16
times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of
the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the
eighth base clock pulse (figure 12.13).
X = Receive data is not transferred from RSR to RDR.
Notes on Use
RDRF
1
0
0
1
1
0
1
SSR Status Flags
ORER
1
0
0
1
1
0
1
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Receive Data
Transfer
RSR
X
O
O
X
X
O
X
RDR
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