HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 64

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.5.1
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The exception service routine start address is fetched from the exception processing vector
5.5.2
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, illegal slot exception
processing starts up when that undefined code is decoded. Illegal slot exception processing also
starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The
processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
3. The exception service routine start address is fetched from the exception processing vector
5.5.3
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The
CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of
illegal slot instructions, however, the program counter value stored is the start address of the
undefined code.
instruction to be executed after the TRAPA instruction.
table that corresponds to the vector number specified in the TRAPA instruction. That address
is jumped to and the program starts executing. The jump that occurs is not a delayed branch.
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump that occurs is not a delayed branch.
Trap Instructions
Illegal Slot Instructions
General Illegal Instructions
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