HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 110

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.2
The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU
has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset.
Channel 0: TMDR0
Channels 1, 2: TMDR1, TMDR2
Bit 5: BFB
0
1
Bit 4: BFA
0
1
Bits 7, 6—Reserved: These bits are reserved. They always read as 1, and cannot be modified.
Bit 5—Buffer Operation B (BFB): Designates whether to use the TGRB register for normal
operation, or buffer operation in combination with the TGRD register. When using TGRD as a
buffer register, no TGRD register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0,
and cannot be modified.
Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal
operation, or buffer operation in combination with the TGRC register. When using TGRC as a
buffer register, no TGRC register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0,
and cannot be modified.
Initial value:
Initial value:
Timer Mode Register (TMDR)
R/W:
R/W:
Bit:
Bit:
—
—
7
1
R
7
1
R
Description
TGRB operates normally (initial value)
TGRB and TGRD buffer operation
Description
TGRA operates normally (initial value)
TGRA and TGRC buffer operation
—
—
6
1
R
6
1
R
BFB
R/W
—
5
0
5
0
R
BFA
R/W
—
4
0
4
0
R
MD3
MD3
R/W
R/W
3
0
3
0
MD2
MD2
R/W
R/W
2
0
2
0
MD1
MD1
R/W
R/W
1
0
1
0
MD0
MD0
R/W
R/W
0
0
0
0
99