HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 208

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5: TE
0
1
Bit 4: RE
0
1
Bit 3: MPIE
0
1
198
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only if the multiprocessor mode bit (MP) in the serial mode register
(SMR) is set to 1 during reception.
Description
Transmitter disabled (initial value). The transmit data register empty bit
(TDRE) in the serial status register (SSR) is locked at 1.
Transmitter enabled. Serial transmission starts when the transmit data
register empty (TDRE) bit in the serial status register (SSR) is cleared to
0 after writing of transmit data into the TDR. Select the transmit format
in the SMR before setting TE to 1.
Description
Receiver disabled (initial value). Clearing RE to 0 does not affect the
receive flags (RDRF, FER, PER, ORER). These flags retain their
previous values.
Receiver enabled. Serial reception starts when a start bit is detected in
the asynchronous mode, or synchronous clock input is detected in the
clock synchronous mode. Select the receive format in the SMR before
setting RE to 1.
Description
Multiprocessor interrupts are disabled (normal receive operation) (initial
value). MPIE is cleared when the MPIE bit is cleared to 0, or the
multiprocessor bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled. Receive-data-full interrupt
requests (RxI), receive-error interrupt requests (ERI), and setting of the
RDRF, FER, and ORER status flags in the serial status register (SSR)
are disabled until data with the multiprocessor bit set to 1 is received.
The SCI does not transfer receive data from the RSR to the RDR, does
not detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in
the SCR are set to 1), and allows the FER and ORER bits to be set.