HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 176

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.2.2
The timer 1 control/status register (T1CSR) is an 8-bit readable/writable* register that selects the
clock to be input to the timer 1 counter (T1CNT) and the timer mode.
Bits 7, 5, and 2 through 0 are initialized to 0 by a power-on reset.
Note: The method for writing to T1CSR is different from that for general registers to prevent
Bit 7: OVF
0
1
Bit 5: TME
0
1
166
Bit 7—Overflow Flag (OVF): Indicates that T1CNT has overflowed from H'FF to H'00.
Bit 6—Reserved: This bit always reads 0 and must only be written with 0.
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bits 4 and 3—Reserved: These bits always read 1 and must only be written with 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock ( ), for input to T1CNT.
Initial value:
inadvertent overwriting. For details, see section 9.2.3, Notes on Register Access.
Timer 1 Control/Status Register (T1CSR)
R/W:
Bit:
Description
No T1CNT overflow (initial value)
[Clearing condition]
Cleared by reading OVF then writing 0 in OVF
[Setting condition]
Set when T1CNT overflows
Description
Timer disabled: T1CNT is initialized to H'00 and halted (initial value)
Timer enabled: T1CNT starts counting, and an interrupt is generated when
T1CNT overflows
R/(W)*
OVF
7
0
—
6
0
R
TME
R/W
5
0
—
4
1
R
—
3
1
R
CKS2
R/W
2
0
CKS1
R/W
1
0
CKS0
R/W
0
0