HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 123

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.7
Each timer general register (TGR) is a 16-bit register that can function as either an output compare
register or an input capture register. There are a total of eight TGR, four each for channels 0 and
two each for channels 1 and 2. The TGRC and TGRD of channels 0 can be set to operate as buffer
registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB
with TGRD.
The TGRs are initialized to H'FFFF by a power-on reset. Accessing of the TGRs in 8-bit units is
disabled; they may only be accessed in 16-bit units.
8.2.8
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–2. TSTR is initialized to H'00 upon power-on reset.
112
Bits 7–3—Reserved. These bits always read 0. The write value should always be 0.
Bits 2–0—Counter Start 2-0 (CST2-CST0): Select starting and stopping of the timer counters
(TCNT). The corresponding between bits and channels is as follows:
CST2: Channel 2 (TCNT2)
CST1: Channel 1 (TCNT1)
CST0: Channel 0 (TCNT0)
Initial value:
Initial value:
Initial value:
Timer General Register (TGR)
Timer Start Register (TSTR)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
R/W
R/W
15
—
1
7
1
7
0
R
R/W
R/W
14
—
1
6
1
6
0
R
R/W
R/W
13
—
1
5
1
5
0
R
R/W
R/W
12
—
1
4
1
4
0
R
R/W
R/W
11
—
1
3
1
3
0
R
CST2
R/W
R/W
R/W
10
1
2
1
2
0
CST1
R/W
R/W
R/W
9
1
1
1
1
0
CST0
R/W
R/W
R/W
8
1
0
1
0
0