HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 207

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 1: CKS1
0
1
12.2.6
The serial control register (SCR) operates the SCI transmitter/receiver, enables/disables interrupt
requests. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a power-
on reset.
Bit 7: TIE
0
1
Bit 6: RIE
0
1
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TxI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI)
requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set
to 1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables
receive-error interrupt (ERI) requests.
Initial value:
Serial Control Register (SCR)
R/W:
Bit:
Bit 0: CKS0
0
1
0
1
R/W
TIE
7
0
Description
Transmit-data-empty interrupt request (TxI) is disabled (initial value).
The TxI interrupt request can be cleared by reading TDRE after it has
been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TxI) is enabled
Description
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are disabled (initial value). RxI and ERI interrupt requests can
be cleared by reading the RDRF flag or error flag (FER, PER, or ORER)
after it has been set to 1, then clearing the flag to 0, or by clearing RIE
to 0.
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are enabled.
R/W
RIE
6
0
Description
/4
/16
/64
(initial value)
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
—
1
0
R
—
0
0
R
197