HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 120
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
- Current page: 120 of 689
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Section 6 User Break Controller (UBC)
6.3.2
On-chip memory (on-chip ROM (SH7034 only) and RAM) is always accessed 32 bits each bus
cycle. Two instructions are therefore fetched in a bus cycle from on-chip memory . Although only
a single bus cycle occurs for the two-instruction fetch, a break can be set on either instruction by
placing the corresponding address in the break address registers (BAR). In other words, to break
the second of the two instructions fetched, set its start address in the BAR. The break will then
occur after the first instruction executes.
6.3.3
Break on Instruction Fetch: The program counter (PC) value saved in user break interrupt
exception processing for an instruction fetch is the address set as the break condition. The user
break interrupt is generated before the fetched instruction is executed. If a break condition is set on
the fetch cycle of a delayed slot instruction immediately following a delayed branch instruction or
on the fetch cycle of an instruction that follows an interrupt-disabling instruction, however, the
user break interrupt is not accepted immediately, so the instruction is executed. The user break
interrupt is not accepted until immediately after that instruction. The PC value that will be saved is
the start address of the next instruction that is able to accept the interrupt.
Break on Data Access (CPU/DMAC): The program counter (PC) value is the top address of the
next instruction after the last executed instruction at the time when the user break exception
processing is activated. When data access (CPU/DMAC) is set as a break condition, the place
where the break will occur cannot be specified exactly. The break will occur at the instruction
fetched close to where the data access that is to receive the break occurs.
Rev. 7.00 Jan 31, 2006 page 92 of 658
REJ09B0272-0700
Break on Instruction Fetch Cycles to On-Chip Memory
Program Counter (PC) Value Saved in User Break Interrupt Exception Processing
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